Registered User mNo edit summary Tag: 2017 source edit |
Registered User No edit summary |
||
(2 intermediate revisions by the same user not shown) | |||
Line 1: | Line 1: | ||
{{ApplicableFor | {{ApplicableFor | ||
|MPUs list=STM32MP25x | |MPUs list=STM32MP25x | ||
|MPUs checklist=STM32MP13x,STM32MP15x,STM32MP25x | |MPUs checklist=STM32MP13x, STM32MP15x, STM32MP21x, STM32MP23x, STM32MP25x | ||
}} | }} | ||
Some typical issues related to the '''PCIe''' feature are listed below. Solutions or debugging methods are proposed for these issues. | Some typical issues related to the '''PCIe''' feature are listed below. Solutions or debugging methods are proposed for these issues. |
Latest revision as of 06:58, 24 October 2024
Some typical issues related to the PCIe feature are listed below. Solutions or debugging methods are proposed for these issues.
If your issue is not listed, try also looking in the articles in the Category:PCIe or troubleshooting grids categories.
Symptom | Resolution |
---|---|
lspci does not show the device, device not enumerated. | A possible issue is that the common reference clock is not started, check that the clkreq# sideband signal correctly toggles to low.
If it remains high, which indicates a nonconformant connection, force the GPIO to low in the device tree pcie_rc node:
&pcie_rc {
- pinctrl-names = "default", "init", "sleep";
- pinctrl-0 = <&pcie_pins_a>;
- pinctrl-1 = <&pcie_init_pins_a>;
- pinctrl-2 = <&pcie_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pcie_init_pins_a>;
+ pinctrl-1 = <&pcie_sleep_pins_a>;
|