Secure context isolation

Applicable for

STM32MP13x lines, STM32MP15x lines, STM32MP21x lines, STM32MP23x lines, STM32MP25x lines

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The STM32 MPUs include set of hardware mechanisms to secure the running software. Depending on the STM32 Arm^® Cortex^® MPUs  family, different isolation management are available.

The following articles focus on the specific management of isolation mechanism per topology:

• Memory isolation
  • TZC internal peripheral on STM32MP1 series
  • ETZPC internal peripheral on STM32MP1 series
  • Resource Isolation Framework overview on STM32MP2 series
• CPU execution level / privilege level isolation
  • Trustzone environment on STM32MP1 series and on STM32MP2 series
• Peripheral isolation
  • ETZPC internal peripheral on STM32MP1 series
  • Resource Isolation Framework overview on STM32MP2 series

Some more complex peripherals directly include security management inside its own registers to manage the isolation level. The secure configuration depends on the global topology used on the MPU family. It is the case for:

• BSEC internal peripheral
• EXTI internal peripheral
• FMC internal peripheral
• GPIO internal peripheral
• HPDMA internal peripheral
• HSEM internal peripheral
• IPCC internal peripheral
• PWR internal peripheral
• RCC internal peripheral
• RTC internal peripheral
• TAMP internal peripheral

Arm^® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Cortex^®

Central processing unit

Microprocessor unit

Arm^® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Cortex^®

Central processing unit

Microprocessor unit